FIGS. 1A through 1D illustrate a conventional two-terminal capacitor. In particular, FIG. 1A is a view of negative capacitor plane 10 including negative plate 11 and negative terminal 12, and FIG. 1B is a view of positive capacitor plane 20 including positive plate 21 and positive terminal 22. FIG. 1C is a side cutaway view of capacitor 30, which shows several alternately stacked planes 10 and 20, with dielectric material 40 disposed therebetween. The negative terminals 12 of each negative plane 10 are electrically coupled, as are the positive terminals 22 of each positive plane 20. FIG. 1D is a top view of capacitor 30, showing a negative terminal 12 and a positive terminal 22 that may be coupled to an electrical circuit.
FIGS. 2A through 2D illustrate a conventional eight-terminal capacitor. FIG. 2A shows negative capacitor plane 50 including negative terminals 52 and voids 55, and FIG. 2B shows positive capacitor plane 60 including positive terminals 62 and voids 65. FIG. 2C is a side cutaway view of capacitor 70, which includes several alternately stacked planes 50 and 60, separated by dielectric material 80. The X's of FIG. 2C indicate a lack of electrical interconnection between a plane and an adjacent vertically-disposed conductor.
Each negative terminal 52 is electrically coupled to a negative terminal 52 located above and/or below it. For example, a conductor may be coupled to a negative terminal 52, pass through a void 65 located directly below the negative terminal 52, and be coupled to a negative terminal 52 located directly below the void. Each positive terminal 62 may be similarly coupled to one or more other positive terminals 62. For example, internal plane 100a is not electrically coupled to terminal 22 of the lowermost plane 20. FIG. 2D is a top view of capacitor 70, showing four negative terminals 52 and four positive terminals 62 that may be coupled to an electrical circuit.
Either or both of the foregoing capacitors may exhibit an Equivalent Series Resistance (ESR) that is unsuitable for some applications. If used as a decoupling capacitor on an integrated circuit package, for example, the ESR of either capacitor may be too low to satisfactorily dampen resonance between an integrated circuit die and a motherboard to which the package is coupled.